Ground bounce problems are prevalent in the design of integrated circuits such as a semiconductor memory device. Noises induced by output buffers of an integrated circuit is common and increases the degree of ground bounce. Transistors of large size, which are included in the output buffer circuit and the package inductance, in particular, cause ground bounce phonomenon.
FIG. 1A shows the configuration of coupling a sending chip 100 to a receiving chip 101. If there are n drivers switching from a high state to a low state and a non-switching driver is holding an output at a low state, a discharge current n.multidot.I.sub.dis flow through the ground terminal of the sending chip 100. The change of electrical current induces a voltage V.sub.L at the inductance L of the ground path which raises the chip internal ground potential, as the relationship between the variables are represented by the following equation: ##EQU1##
The condition described above may cause several effects. First, the signal at the output of the switching driver will be delayed due to the drop of the effective power supply voltage. Thus, the output signal becomes valid later. Second, a disturbance signal will be coupled to the output of the non-switching driver. The disturbance can exceed the threshold voltage of the receiver chip 101. Third, the resulting fluctuation of the chip internal power supply and ground potential can cause malfunction of a chip internal logic. Last, the undershoots at the outputs can damage the input circuit of the receiver chip 101.
In FIG. 1B, there is shown a prior art circuit diagram of a conventional CMOS output buffer. The output buffer circuit includes a pull-up transistor device 110, and a pull-down transistor device 111, connected in series between the internal power supply node and internal ground potential node. There are three package inductors Lp 112, Lg 113 and Ld 114.
In FIG. 1C, there is shown a prior art circuit diagram for a conventional NMOS output buffer. The NMOS output buffer includes a pull-up transistor device 120, and a pull-down transistor device 121, connected in series between the internal power supply node and internal ground potential node. To produce a full V.sub.dd output high logic level signal at the output terminal, the pull-up N-channel output transistor 120 must receive a boosted gate signal at least one transistor threshold value above V.sub.dd supply voltage.
The semiconductor memory device employs a byte-wide memory scheme for accessing more data during one operation cycle, and therefore, a plurality of output buffers are simultaneously enabled to realize the byte-wide output organization. Accordingly, since a plurality of output buffer is simultaneously operated, the problems caused by ground bounce become more severe. Two different output drive design methodologies are often used in the design of integrated circuits: 1) current controlled output driver, and 2) controlled slew rate output driver. Simulations have demonstrated that the use of a current controlled output driver degrades the switching speed for clock frequencies of 30 MHz or greater. The objective of a controlled slew rate output driver is to control the output driver's rise and fall times in order to control the ground bounce (di/dt) noise. It is the objective of the invention to provide a controlled slew rate output driver circuit in order to reduce ground bounce noise.